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march 2011 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 fan5354 3mhz, 3a synchronous buck regulator fan5354 3mhz, 3a synchronous buck regulator features 3mhz fixedfrequency operation bestinclass load transient 3a output current capability 2.7v to 5.5v input voltage range adjustable output voltage: 0.8 to v in ?0.9 pfm mode for high efficiency in light load (forced pwm available on mode pin) minimum pfm frequency avoids audible noise 270a typical quiescent current in pfm mode external frequency synchronization low ripple lightload pfm mode with forced pwm control power good output internal softstart input undervoltage lockout (uvlo) thermal shutdown and overload protection 12lead 3x3.5mm mlp applications settop box hard disk drive communications cards dsp power description the fan5354 is a stepdown switching voltage regula tor that delivers an adjustable output from an input voltage supply of 2.7v to 5.5v. using a proprietary architecture with synchronous rectification, the fan5354 is capable o f delivering 3a at over 85% efficiency, while maintai ning a very high efficiency of over 80% at load currents a s low as 2ma. the regulator operates at a nominal fixed freq uency of 3mhz, which reduces the value of the external compo nents to 470nh for the output inductor and 10f for the o utput capacitor. additional output capacitance can be add ed to improve regulation during load transients without a ffecting stability and inductance up to 1.2h may be used wi th additional output capacitance. at moderate and light loads, pulse frequency modula tion (pfm) is used to operate the device in powersave m ode with a typical quiescent current of 270a. even wit h such a low quiescent current, the part exhibits excellent transient response during large load swings. at higher loads, the system automatically switches to fixedfrequency co ntrol, operating at 3mhz. in shutdown mode, the supply cur rent drops below 1a, reducing power consumption. pfm mo de can be disabled if constant frequency is desired. t o avoid audible noise, the regulator limits its minimum pfm frequency. the fan5354 is available in 12lead 3x3. 5mm mlp package. figure 1. typical application ordering information part number temperature range package packing metho d fan5354mpx 40 to 85c mlp12, 3x3.5mm tape and reel
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 2 fan5354 3mhz, 3a synchronous buck regulator table 1. recommended external components for 3a max imum load current component description vendor parameter typ. units l1 470nh nominal ihlp1616aber47m01 (vishay) sd12r47r (coiltronics) vlc5020tr47n (tdk) (tdk) lqh55pnr47nt0 (murata) l 0.47 h dcr 20 m c out 2 pieces 10 f, 6.3v, x5r, 0805 grm21br60j106m (murata) c2012x5r0j106m (tdk) c 10.0 f c in 10 f, 6.3v, x5r, 0805 c in1 10nf, 25v, x7r, 0402 grm155r71e103k (murata) c1005x7r1e103k (tdk) c 10 nf c vcc 4.7 f, 6.3v, x5r, 0603 grm188r60j475k (murata) c1608x5r0j475k (tdk) c 4.7 f r3 (1) resistor: 1 0402 any r 1 note: 1. r3 is optional and improves ic power supply nois e rejection. see layout recommendations for more information. pin configuration fb vout pgnd pgnd sw sw mode pgood en vcc pvin pvin 6 5 4 3 2 1 7 8 9 10 11 12 p1 (gnd) figure 2. 12pin, 3x3.5mm mlp (top view) pin definitions pin # name description 1 fb fb . connect to resistor divider. the ic regulates thi s pin to 0.8v. 2 vout vout . sense pin for vout. connect to cout. 3, 4 pgnd power ground . lowside mosfet is referenced to this pin. cin an d cout should be returned with a minimal path to these pins. 5, 6 sw switching node . connect to inductor . p1 gnd ground. all signals are referenced to this pin. 7, 8 pvin power input voltage . connect to input power source. connect to cin wit h minimal path. 9 vcc ic bias supply . connect to input power source. use a separate byp ass capacitor cvcc from this pin to the p1 gnd terminal between pins 1 and 12. 10 en enable . the device is in shutdown mode when this pin is l ow. do not leave this pin floating. 11 pgood power good . this opendrain pin pulls low if the output falls out of regulation or is in softstart. 12 mode mode / sync . a logic 0 allows the ic to automatically switch t o pfm during light loads. when held high, the ic to stays in pwm mode. the regulator al so synchronizes its switching frequency to the frequency provided on this pin. do not leave this p in floating. note: 2. p1 is the bottom heatsink pad. ground plane sho uld flow through pins 3, 4, and p1 and can be exten ded through pin 11 if pgoods function is not required, and through pin 1 2 if mode is to be grounded, to improve ic cooling.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 3 fan5354 3mhz, 3a synchronous buck regulator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in ad dition, extended exposure to stresses above the recommended operatin g conditions may affect device reliability. the abs olute maximum ratings are stress ratings only. symbol parameter min. max. units v in sw, pvin, vcc pins ic not switching 0.3 7.0 v ic switching 0.3 6.5 other pins 0.3 v cc + 0.3 (3) v v inov_slew maximum slew rate of vin above 6.5v when pwm is swi tching 15 v/ms r pgood pullup resistance from pgood to vcc 1 k esd electrostatic discharge protection level human body model per jesd22a114 2 kv charged device model per jesd22c101 2 t j junction temperature C40 +150 c t stg storage temperature C65 +150 c t l lead soldering temperature, 10 seconds +260 c note: 3. lesser of 7v or v cc +0.3v. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recomme nded operating conditions are specified to ensure optimal performa nce to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum rat ings. symbol parameter min. typ. max. units v cc, v in supply voltage range 2.7 5.5 v v out output voltage range 0.8 90% duty cycle v i out output current 0 3 a l inductor 0.47 h c in input capacitor 10 f c out output capacitor 20 f t a operating ambient temperature 40 +85 c t j operating junction temperature 40 +125 c thermal properties symbol parameter min. typ. max. units ja junctiontoambient thermal resistance (4) 46 c/w note: 4. junctiontoambient thermal resistance is a func tion of application and board layout. this data is measured with fourlayer 1s2p boards in accordance to jesd51 jedec standard . special attention must be paid not to exceed junc tion temperature t j(max) at a given ambient temperate t a .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 4 fan5354 3mhz, 3a synchronous buck regulator electrical characteristics minimum and maximum values are at v in =2.7v to 5.5v, t a =40c to +85c, unless otherwise noted. typical va lues are at t a =25c, v in =5v. symbol parameter conditions min. typ. max. units power supplies i q quiescent current i load =0, mode=0 270 a i load =0, mode=1 (forced pwm) 14 ma i sd shutdown supply current en=gnd 0.1 3.0 a v uvlo undervoltage lockout threshold v in rising 2.83 2.95 v v in falling 2.10 2.30 2.40 v v uvhyst undervoltage lockout hysteresis 530 mv logic pins v ih highlevel input voltage 1.05 v v il lowlevel input voltage 0.4 v v lhyst logic input hysteresis voltage 100 mv i in input bias current input tied to gnd or v in 0.01 1.00 a i outl pgood pulldown current v pgood =0.4v 1 ma i outh pgood high leakage current v pgood =v in 0.01 1.00 a v out regulation v ref output reference dc accuracy measured at fb pin t a =25c 0.792 0.800 0.808 v 0.788 0.800 0.812 v v reg v out dc accuracy at v out pin w.r.t. calculated value, i load =500ma 1.6 +1.6 % load out i v load regulation i out(dc) =1 to 3a C0.03 %/a in out v v line regulation 2.7v v in 5.5v, i out(dc) =1.5a 0.01 %/v transient response i load step 0.1a to 1.5a, t r =t f =100ns, v out =1.2v + 40 mv power switch and protection r ds(on)p pchannel mosfet on resistance 60 m r ds(on)n nchannel mosfet on resistance 40 m i limpk pmos peak current limit 3.75 4.55 5.50 a t limit thermal shutdown 150 c t hyst thermal shutdown hysteresis 20 c v sdwn input ovp shutdown rising threshold 6.2 v falling threshold 5.50 5.85 v frequency control f sw oscillator frequency 2.7 3.0 3.3 mhz f sync mode pin synchronization range external squarewav e, 30% to 70% duty cycle 2.7 3.0 3.3 mhz f pfm(min) minimum pfm frequency t a = 25c, v in = 5.0v 17 26 36 khz softstart t ss regulator enable to regulated v out r load > 5 , to v out =1.2v 210 250 s r load > 5 , to v out =1.8v 340 420 s v slew softstart v ref slew rate 10 v/ms
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 5 fan5354 3mhz, 3a synchronous buck regulator typical characteristics unless otherwise specified, v in =5v, v out =1.2v, circuit of figure 1, and components per tabl e 1. 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1 10 100 1000 10000 efficiency i load output current (ma) vin = 3.3v, mode=0 vin = 3.3v, mode=1 vin = 5v, mode=0 vin = 5v, mode=1 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1 10 100 1000 10000 i load output current (ma) efficiency vin = 3.3v, mode = 0 vin = 3.3v, mode = 1 vin = 5v, mode = 0 vin = 5v, mode = 1 figure 3 . efficiency vs. i load at v out =1.2v figure 4 . efficiency vs. i load at v out = 1.8v 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1 10 100 1000 10000 i load output current (ma) efficiency vin = 3.3v, mode = 0 vin = 3.3v, mode = 1 vin = 5v, mode = 0 vin = 5v, mode = 1 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1 10 100 1000 10000 i load output current (ma) efficiency vin = 4.2v, mode = 0 vin = 4.2v, mode = 1 vin = 5v, mode = 0 vin = 5v, mode = 1 figure 5 . efficiency vs. i load at v out = 2.5v figure 6 . efficiency vs. i load at v out = 3.3v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2.7 3.2 3.7 4.2 4.7 5.2 input voltage(v) supply current ( a) 85c 25c -40c 200 225 250 275 300 325 350 375 400 2.7 3.2 3.7 4.2 4.7 5.2 input voltage(v) pfm, no load supply current(a) 85c 25c C40c vout = 1.2 vout = 3.3 figure 7. shutdown supply current vs v in , en=0 figure 8. quiescent current in pfm vs. v in , no load
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 6 fan5354 3mhz, 3a synchronous buck regulator typical characteristics unless otherwise specified, v in =5v, v out =1.2v, circuit of figure 1, and components per tabl e 1. 0 100 200 300 400 500 600 700 800 900 1000 2.7 3.2 3.7 4.2 4.7 5.2 load current (ma) input voltage(v) 1.2vout boundary 1.2vout boundary 3.3vout boundary 3.3vout boundary always pwm always pfm hysteresis 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1 1.5 2 2.5 3 load current (a) switching frequency (mhz) vin = 4.1v vin = 4.0v vin = 3.9v vin = 3.8v figure 9 . pfm/pwm mode c hange b oundaries figure 10 . effect of t off m in imum on r educing switching frequency at large duty cycles, v out =3.3v 0 2 4 6 8 10 12 14 16 0.1 1 10 100 1000 10000 load current(ma) vout ripple (mvac pp) 5vin, 1.2vout 3.3vin, 1.2vout 5vin,3.3vout pfm pwm 20 30 40 50 60 70 80 90 0.01 0.1 1 10 100 frequency (khz) psrr attenuation (db) 1.2vout,1.5a load 3.3vout, 0.5a load in pfm 3.3vout, 1.5a load figure 11 . output voltage r ipple vs. load current (see explanation on page 12) figure 12 . power supply rejection ratio (psrr) v out i l figure 13 . pfm to pwm m ode t ransition, s lowly increasing load current, 2s/div. f igure 14 pwm to pfm m ode t ransition, slowly decreasing load current, 2s/div.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 7 fan5354 3mhz, 3a synchronous buck regulator typical characteristics unless otherwise specified, v in =5v, v out =1.2v, circuit of figure 1, and components per tabl e 1. 24.0 25.0 26.0 27.0 28.0 29.0 30.0 31.0 2.5 3 3.5 4 4.5 5 5.5 6 switching frequency (khz) input voltage (v) tj = 85 c tj = 25c tj = C40c figure 15. pfm frequency, i load = 0 load transient response (figure 16 C figure 19). i load t r = t f = 100ns figure 16. mode=0, 100ma to 1.5a to 100ma, 5s/div. figure 17. 500ma to 3a to 500ma, 5s/div. v out i l i load figure 18. mode=1, 100ma to 1.5a to 100ma, 5s/div. figure 19. 24ma to 500ma to 24ma, mode=0, 5s/div.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 8 fan5354 3mhz, 3a synchronous buck regulator typical characteristics unless otherwise specified, v in =5v, v out =1.2v, circuit of figure 1, and components per tabl e 1. i supply v pg v out v en v in =v en v out v pg i supply figure 20. softstart, en voltage raised after v in =5v, i load =0, 100 s/div. figure 21. softstart, en pin tied to vcc i load =0, 1ms/div. figure 22. softstart, en pin raised after v in =5v r load =400m , c out =100 f, 100 s/div. figure 23. softstart, en pin tied to vcc r load =400m , c out =100 f, 1ms/div. figure 24. line transient response in pwm mode, 10 s/div. figure 25. line transient response in pfm mode, 10 s / div.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 9 fan5354 3mhz, 3a synchronous buck regulator typical characteristics unless otherwise specified, v in =5v, v out =1.2v, circuit of figure 1, and components per tabl e 1. circuit protection response v out v pg i l v pg i l v out figure 26. vout to gnd short circuit, 200 s/div. figure 27. vout to gnd short circuit, 5 s/div. v pg v en i l v out v out i l v pg figure 28. overcurrent at startup, r load =200m , 50 s/div. figure 29. progressive overload, 200 s/div.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 10 fan5354 3mhz, 3a synchronous buck regulator operation description the fan5354 is a stepdown switching voltage regula tor that delivers an adjustable output from an input voltage supply of 2.7v to 5.5v. using a proprietary architecture with synchronous rectification, the fan5354 is capable o f delivering 3a at over 80% efficiency. the regulator operates at a nominal frequency of 3mhz at full load, which reduces the value of the external components to 470nh for t he output inductor and 20f for the output capacitor. high ef ficiency is maintained at light load with singlepulse pfm mode . control scheme the fan5354 uses a proprietary nonlinear, fixedfr equency pwm modulator to deliver a fast load transient resp onse, while maintaining a constant switching frequency ov er a wide range of operating conditions. the regulator perfor mance is independent of the output capacitor esr, allowing f or the use of ceramic output capacitors. although this typ e of operation normally results in a switching frequency that varies with input voltage and load current, an inte rnal frequency loop holds the switching frequency consta nt over a large range of input voltages and load currents. for very light loads, the fan5354 operates in disco ntinuous current (dcm) singlepulse pfm mode, which produces low output ripple compared with other pfm architectures . transition between pwm and pfm is seamless, with a glitch of less than 18mv at v out during the transition between dcm and ccm modes. the regulator limits minimum pfm frequency to typically26khz. pfm mode can be disabled by holding the mode pin hi gh. the ic synchronizes to the mode pin frequency. when synchronizing to the mode pin, pfm mode is disabled . setting the output voltage the output voltage is set by the r1, r2, and v ref (0.8v): ref ref out v v v 2 r 1 r ? = (1) r1 must be set at or below 100k; therefore: ( ) 8.0 v 8.0 1 r 2 r out ? ? = (2) for example, for v out =1.2v, r1=100k, r2=200k. enable and soft start when the en pin is low, the ic is shut down, all in ternal circuits are off, and the part draws very little cu rrent. raising en above its threshold voltage activates the part a nd starts the softstart cycle. during softstart, the modula tors internal reference is ramped slowly to minimize any large su rge currents on the input and prevents any overshoot of the output voltage. if large values of output capacitance are used, the regulator may fail to start. if v out fails to achieve regulation within 320 s from the beginning of softstart, the regulator s huts down and waits 1200 s before attempting a restart. if the regulator is at its current limit for more than abo ut 60 s, the regulator shuts down before restarting 1200 s later. this limits the c out capacitance when a heavy load is applied during the startup. for a typical fan5354 starting with a resistive load: ) a ( i 100 400 ) f ( cout load max ? ? where load out load r v i = (3) synchronous rectification is inhibited during soft start, allowing the ic to start into a precharged load. mode pin C external frequency synchronization logic 1 on this pin forces the ic to stay in pwm mo de. a logic 0 allows the ic to automatically switch to pf m during light loads. if the mode pin is toggled, the conver ter synchronizes its switching frequency to the frequen cy on the mode pin (f mode ). the mode pin is internally buffered with a schmitt trigger, which allows the mode pin to be driven with slow ri se and fall times. an asymmetric duty cycle for frequency synchronization is permitted as long as the minimum time below v il(max) or above v ih(max) is 100ns. pgood pin the pgood pin is an opendrain that pin indicates t hat the ic is in regulation when its state is open. pgood p ulls low under the following conditions: 1. the ic has operated in cyclebycycle current li mit for eight or more consecutive pwm cycles. 2. the circuit is disabled, either after a fault oc curs, or when en is low. 3. the ic is performing a softstart. undervoltage lockout when en is high, the undervoltage lockout keeps th e part from operating until the input supply voltage rises high enough to properly operate. this ensures no misbeha vior of the regulator during startup or shutdown. input overvoltage protection (ovp) when v in exceeds v sdwn (about 6.2v) the ic stops switching to protect the circuitry from internal spikes above 6.5v. an internal 40 s filter prevents the circuit from shutting down due to noise spikes. for the circuit to fully prote ct the internal circuitry, the v in slew rate above 6.2v must be limited to no more than 15v/ms when the ic is switching. the ic protects itself if v in overshoots to 7v during initial powerup as long as the v in transition from 0 to 7v occurs in less than 10 s (10% to 90%). current limiting a heavy load or short circuit on the output causes the current in the inductor to increase until a maximum current threshold is reached in the highside switch. upon reaching t his point, the highside switch turns off, preventing high cur rents from causing damage. 16 consecutive pwm cycles in curren t limit
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 11 fan5354 3mhz, 3a synchronous buck regulator cause the regulator to shut down and stay off for a bout 1200 s before attempting a restart. in the event of a short circuit, the softstart cir cuit attempts to restart and produces an overcurrent fault after ab out 50 s, which results in a duty cycle of less than 10%, pro viding current into a short circuit. thermal shutdown when the die temperature increases, due to a high l oad condition and/or a high ambient temperature, the ou tput switching is disabled until the temperature on the die has fallen sufficiently. the junction temperature at wh ich the thermal shutdown activates is nominally 150c with a 20c hysteresis. minimum offtime effect on switching frequency t on(min) and t off(min) are both 45ns. this imposes constraints on the maximum vin vout that the fan5354 can provide, while still maintaining a fixed switching frequency in pwm mode. while regulation is unaffected, the switching frequency will drop when the regulator cannot provi de sufficient duty cycle at 3 mhz to maintain regulati on. the calculation for switching frequency is given be low ? ?? ? ? ?? ? = ns 3. 333 1 , t 1 min f ) max ( sw sw where ? ?? ? ? ?? ? ? ? ? ? + + ? = out on out in off out out ) max ( sw v r i v r i v 1 ns 45 t off r = l n _ dson dcr r + on r = l p _ dson dcr r + (4) application information selecting the inductor the output inductor must meet both the required ind uctance and the energy handling capability of the applicati on. the inductor value affects the average current limit, t he output voltage ripple, and the efficiency. the ripple current (?i) of the regulator is: ? ?? ? ? ?? ? ? ? ? sw out in in out f l v v v v i (5) the maximum average load current, i max(load) is related to the peak current limit, i lim(pk) , by the ripple current as: 2 i i i ) pk ( lim ) load ( max ? = (6) the fan5354 is optimized for operation with l=470nh , but is stable with inductances up to 1.2 h (nominal). the inductor should be rated to maintain at least 80% o f its value at i lim(pk) . failure to do so lowers the amount of dc current the ic can deliver. efficiency is affected by the inductor dcr and indu ctance value. decreasing the inductor value for a given ph ysical size typically decreases the dcr; but since ?i incr eases, the rms current increases, as do core and skineffect l osses. 12 i i i 2 2 ) dc ( out rms + = (7) the increased rms current produces higher losses th rough the r ds(on) of the ic mosfets as well as the inductor esr. increasing the inductor value produces lower rms cu rrents, but degrades transient response. for a given physic al inductor size, increased inductance usually results in an inductor with lower saturation current. table 2 shows the effects of inductance higher or l ower than the recommended 470nh on regulator performance. table 2. effects of increasing the inductor value (from 470nh recommended) on regulator performance i max(load) ?v out (eq. 8) transient response increase decrease degraded inductor current rating the fan5354s current limit circuit can allow a pea k current of 5.5a to flow through l1 under worstcase conditi ons. if it is possible for the load to draw that much continuous current, the inductor should be capable of sustaining that c urrent or failing in a safe manner. for spaceconstrained applications, a lower current rating for l1 can be used. the fan5354 may still protect these inductors in the event of a short circuit, but may not be able to protect the inductor from failure if the load is able to draw higher currents than the dc rating of the inductor. output capacitor and v out ripple note: table 1 suggests 0805 capacitors, but 0603 capacito rs may be used if space is at a premium. due to voltage ef fects, the 0603 capacitors have a lower incircuit capacitance than the 0805 package, which can degrade transient response and output ripple. increasing c out has no effect on loop stability and can therefore be increased to reduce output voltage rip ple or to improve transient response. output voltage ripple, ?v out , is: ? ?? ? ? ?? ? + ? ? ? = esr f c 8 1 i v sw out out (8) where c out is the effective output capacitance. the capacitance of c out decreases at higher output voltages, which results in higher ?v out . if c out is greater than 100 f, the regulator may fail to start under load. if an inductor value greater than 1.0 h is used, at least 30 f of c out should be used to ensure stability.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 12 fan5354 3mhz, 3a synchronous buck regulator as can be seen in figure 11 the lowest ?v out is obtained when the ic is in pwm mode and, therefore, operatin g at 3mhz. in pfm mode, f sw is reduced, causing ?v out to increase. at extremely light loads, the output ripp le decreases, as the minimum frequency circuit becomes active and the effective t on (highside ontime) decreases. esl effects the esl (equivalent series inductance) of the outpu t capacitor network should be kept low to minimize th e square wave component of output ripple that results from t he division ratio c out esl and the output inductor (l out ). the square wave component due to the esl can be estimated as: 1 l esl v v cout in ) sq ( out ? (9) a good practice to minimize this ripple is to use m ultiple output capacitors to achieve the desired c out value. for example, to obtain c out =20 f, a single 22 f 0805 would produce twice the square wave ripple of 2 x 10 f 0805. to minimize esl, try to use capacitors with the low est ratio of length to width. 0805s have lower esl than 1206s . if low output ripple is a chief concern, some vendors prod uce 0508 or 0612 capacitors with ultralow esl. placing addi tional small value capacitors near the load also reduces t he high frequency ripple components. input capacitor the 10 f ceramic input capacitor should be placed as close as possible between the vin pin and pgnd to minimiz e the parasitic inductance. if a long wire is used to bri ng power to the ic, additional bulk capacitance (electrolytic or tantalum) should be placed between c in and the power source lead to reduce underdamped ringing that can occur between the inductance of the power source leads and c in . the effective c in capacitance value decreases as v in increases due to dc bias effects. this has no signi ficant impact on regulator performance. layout recommendations the layout recommendations below highlight various top copper planes by using different colors. it include s cout3 to demonstrate how to add c out capacitance to reduce ripple and transient excursions. the inductor in this exam ple is the tdk vlc5020tr47n. vcc and vin should be connected together by a thin trace some distance from the ic, or through a resistor (s hown as r3 below), to isolate the switching spikes on pvin from the ics bias supply on vcc. if pcb area is at a premiu m, the connection between pvin and vcc can be made on anot her pcb layer through vias. the via impedance provides some filtering for the highfrequency spikes generated o n pvin. pgnd and agnd connect through the thermal pad of th e ic. extending the pgnd and agnd planes improves ic cool ing. the ic analog ground (agnd) is bonded to p1 between pins 1 and 12. large ac ground currents should return to pins 3 and 4 (pgnd) either through the copper under p1 bet ween pins 6 and 7 or through a direct trace from pins 3 and 4 (as shown for cout1cout3). en and pgood connect through vias to the system con trol logic. cin1 is an optional device used to provide a lower impedance path for highfrequency switching edges/s pikes, which helps to reduce sw node and vin ringing. cin should be placed as close as possible between pgnd and vin as shown below. pgnd connection back to inner planes should be accomplished as series of vias distributed among th e cout return track and cin return plane between pins 6 an d 7. vcc vout sw agnd pgnd vin 10 f 0805 0402 0402 0402 cin1 cin 0603 cvcc l1 0.47 h 5 x 5 mm 10 f 0805 cout2 10 f 0805 cout1 10 f 0805 cout3 0402 r3 pgnd 6 5 4 3 2 1 7 8 9 10 11 12 p1 (gnd) fan5354 figure 30. 3a layout recommendation
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 13 fan5354 3mhz, 3a synchronous buck regulator physical dimensions figure 31. 12lead 3 x 3.5mm mlp package drawings are provided as a service to custo mers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor repr esentative to verify or obtain the most recent revision. package specifications do not expa nd the terms of fairchilds worldwide terms and con ditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5354 ? rev. 1.0.5 14 fan5354 3mhz, 3a synchronous buck regulator

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